1. Technical Field
The present disclosure relates to a semiconductor memory device, and more particularly, to a semiconductor memory device which allocates memory banks having memory cells storing data for detecting data errors, correcting data errors, and enhancing the yield of a semiconductor chip.
2. Discussion of the Related Art
Rapid progress in semiconductor technology development has resulted in high integration and high performance semiconductor integrated circuits, and in particular, remarkably high integration has been attained in the field of semiconductor memory devices.
However, due to the high performance of a semiconductor integrated circuit, when the size of the semiconductor chip increases, the yield of the semiconductor chip decreases in proportion to the increase in size. Moreover, increasing the degree of integration further decreases the yield of the semiconductor chip. A defect relief circuit can be built in a semiconductor chip of a semiconductor memory device to increase the yield.
The defect relief circuit can make use of an Error Correction Code (ECC) to store main data and parity data generated within the semiconductor memory. A Hamming Code is an ECC that may be employed for digital communication to detect and correct errors using a parity bit.
ECCs have been increasingly applied to non-volatile memory devices requiring high reliability such as a mask Read Only Memory (ROM) or an Electrically Erasable and Programmable Read Only Memory (EEPROM).
Applying an ECC to a non-volatile memory device may cause an increase in chip size due to the addition of a parity cell or a speed delay on the error correction circuit. However, such applications may enhance reliability and yield.
FIG. 1 is a schematic block diagram of a conventional semiconductor memory device, which includes an address input buffer 10, a command decoder 12, a plurality of memory banks BA_A, BA_B, BA_C and BA_D, a plurality of row address decoders 20-1, 20-2, 20-3 and 20-4, a plurality of column address decoders 30-1, 30-2, 30-3 and 30-4, a data input buffer 40, a parity data generation unit 42, a data input driver 44, an output multiplexer 50, a data error detection and correction unit 52, and a data output buffer 54.
Each of the plurality of memory banks includes normal memory cells 60-1, 60-2, 60-3 and 60-4, and ECC memory cells 70-1, 70-2, 70-3 and 70-4. For ease of discussion, it is assumed that the plurality of memory banks are four memory banks BA_A, BA_B, BA_C and BA_D.
The address input buffer 10 receives and buffers an external address ADD in response to an active signal ACT and a clock signal PCLK during an active operation to generate an internal row address ra[14:0], and receives and buffers an external address ADD in response to a write signal WE or a read signal RE and a clock signal PCLK during a write or read operation to generate an internal column address ca[14:0].
The command decoder 12 receives a command signal CMD and decodes the command signal CMD in response to a clock signal PCLK to generate the active signal ACT, the write signal WE, and the read signal RE.
Each of the plurality of row address decoders 20-1, 20-2, 20-3 and 20-4 receives an internal row address ra[14:0] and an active signal ACT, and decodes the signals to activate one signal WL_A, WL_B, WL_C and WL_D among word selection signals of each of the four memory banks BA_A, BA_B, BA_C and BA_D.
Each of the plurality of column address decoders 30-1, 30-2, 30-3 and 30-4 receives and decodes the buffered internal column address ca[14:0] and the active signal ACT to activate one signal CSL_A, CSL_B, CSL_C and CSL_D among column selection signals of each of the four memory banks BA_A, BA_B, BA_C and BA_D.
Each of the memory banks BA_A, BA_B, BA_C and BA_D, in response to the data write signal WE or the data read signal RE, inputs normal data to the normal memory cells 60-1, 60-2, 60-3 and 60-4, or outputs the normal data from the normal data cells 60-1, 60-2, 60-3 and 60-4 and inputs parity data to the ECC memory cells 70-1, 70-2, 70-3 and 70-4, or outputs the parity data from the ECC memory cells 70-1, 70-2, 70-3 and 70-4.
The data input buffer 40 receives and buffers write data Di of N bits through data input and output pins in response to the write signal WE and the clock signal PCLK to output buffered write data.
The parity data generation unit 42 receives and encodes the write data buffered by the data input buffer 40 to generate parity data, thereby outputting normal write data of N bits and parity write data of M bits.
The output multiplexer 50 receives and multiplexes normal read data of N bits and parity read data of M bits from the plurality of memory banks in response to the data read signal RE, and then outputs them.
The data error detection and correction unit 52 receives and decodes the normal read data of N bits and the parity read data of M bits output from the output multiplexer 50, and then restores the normal read data and the parity read data to original read data of N bits to output them. The restored read data is subjected to a Hamming Code algorithm for detecting errors, and data with errors are corrected.
The data output buffer 54 receives read data of N bits from the data error detection and correction unit 52, and delays the read data by a predetermined time to output the buffered read data through the data input and output pins.
It is assumed that the plurality of word line selection signals are n bits, the plurality of column selection signals are m bits, and the write data Di and the read data Do are K serial data converted to/from parallel data of N bits.
When a row address ra[14:0] of 15 bits is externally applied with predetermined commands, the command decoder 12 internally generates an active command ACT, and the address input buffer 10 buffers a row address RA in response to a buffered clock signal PCLK to generate a buffered internal row address ra[14:0] of 15 bits.
Each of the plurality of row address decoders 20-1, 20-2, 20-3 and 20-4 decodes 13 bits ra[12:0] of the internal row address ra[14:0] to generate word line selection signals, so that one selection signal of the word line selection signals is activated. Two most significant bits ra[14:13] are decoded as a bank address to select a memory bank. The combinations of the two most significant bits are ‘00’, ‘01’, ‘10’, and ‘11’, for respectively selecting corresponding banks BA_A, BA_B, BA_C and BA_D during a data write operation.
When a column address ca[14:0] of 15 bits is externally applied with predetermined commands, the command decoder 12 generates a write command WE, and the address input buffer 10 buffers a column address CA in response to the buffered clock signal PCLK to generate a buffered column address of 15 bits ca[14:0].
Each of the plurality of column address decoders 30-1, 30-2, 30-3 and 30-4 decodes 13 bits ca[12:0] of the buffered internal column address ca[14:0] to generate a plurality of column selection signals, so that one of the column selection signals is activated. In addition, two most significant bits ca[14:13] are decoded as a bank address to select the memory bank as in the plurality of row address decoders 20-1, 20-2, 20-3 and 20-4.
For example, when the applied bank address is “00”, the first memory bank BA_A of the plurality of memory banks is selected.
The data input buffer 40 receives and buffers write data Di of N bits through data input and output pins in response to the write signal WE and the clock signal PCLK to output buffered write data.
The parity data generation unit 42 receives the write data of N bits buffered by the data input buffer 40 to generate and encode parity data. The parity data generation unit 42 then divides normal write data of N bits and parity write data of M bits to input the normal write data of N bits to the normal memory cell 60-1 of the first memory bank, and input the parity write data of M bits to the ECC memory cells 70-1, 70-2, 70-3 and 70-4 of the first memory bank.
The bank addresses, i.e., ‘01’, ‘10’, and ‘11’, are respectively applied to select the second, third and fourth memory banks BA_B, BA_C and BA_D of the memory banks so that normal write data and parity write data are input to the normal memory cells 60-1, 60-2, 60-3 and 60-4 and the ECC memory cells 70-1, 70-2, 70-3 and 70-4 of the memory banks, respectively.
When a row address of 15 bits RA is externally applied with predetermined commands, an operation is carried out to activate one of the word line selection signals, and two most significant bits ca[14:13] are used as a bank address and then decoded to select the memory bank within the memory cell array.
When a column address of 15 bits CA is externally applied with predetermined commands, the command decoder 12 generates a read command RE, and the address input buffer 10 buffers the column address CA in response to the buffered clock signal PCLK to thereby generate a buffered internal column address of 15 bits ca[14:0].
Each of the plurality of column address decoders 30-1, 30-2, 30-3 and 30-4 decodes 13 bits ca[12:0] of the buffered internal column address ca[14:0] to generate column selection signals, so that one of the column selection signals is activated. Two most significant bits ca[12:0] are used as a bank address to select the memory bank within the memory cell array, as in the operation of the plurality of row address decoders 20-1, 20-2, 20-3 and 20-4.
For example, the first memory bank BA_A is selected among the memory banks when the bank address is ‘00’, such as during a data write operation.
The output multiplexer 50 receives and multiplexes normal read data of N bits and parity read data of M bits from the first memory bank in response to the data read signal RE, and then outputs them.
The data error detection and correction unit 52 simultaneously receives and decodes the normal read data of N bits and the parity read data of M bits output from the output multiplexer 50 to restore the normal read data and the parity read data to original read data Do of N bits and output them. The restored read data Do is subjected to a Hamming Code algorithm for detecting and correcting errors.
The data output buffer 54 receives the read data of N bits from the data error detection and correction unit 52 and delays them by a predetermined time to output the buffered read data Do through data input and output pins
The second to fourth memory banks BA_B, BA_C and BA_D are selected among the memory banks by respectively applying bank addresses such as ‘01’, ‘10’, and ‘11’, so that normal read data and parity read data are output from the respective normal memory cells 60-1, 60-2, 60-3 and 60-4 and the respective ECC memory cells 70-1, 70-2, 70-3 and 70-4. The normal read data of N bits and the parity read data of M bits are multiplexed by the output multiplexer 50, and then subjected to a Hamming Code algorithm for detecting errors while the normal read data and the parity read data are decoded to the original read data Do of N bits, and data having errors is corrected by the data error detection and correction unit 52.
In a conventional semiconductor memory device, where an ECC memory cell is separately disposed in each memory bank, the effect of data error detection and correction may be significant. However, an overhead problem may be caused due to the addition in error detection and correction of all data.
In addition, the Soft Error Rate (SER) may increase due to a change in electrostatic capacitance of capacitors within the memory cell when the semiconductor memory device is exposed to various electromagnetic waves in its packaged state.
A defect relief circuit such as a redundant data error detection and correction circuit can be employed to improve the SER, however, the overhead is significantly increased due to the addition of error detection and correction circuits for all the data in a conventional semiconductor memory device having a conventional memory bank structure.